U.S. Pat. No. 4,486,826 is representative of many prior art patents disclosing a fault tolerant computer system having two identical buses. The buses provide redundancy in case one of the buses should fail. The present invention uses several processing buses, not for reasons of safety (redundancy), but rather to increase performance so that commercial off-the-shelf (COTS) computers can be adapted to process high speed telemetry.
Stowe, M. T., "Modular System Design for Space Station Data Handling Requirements", Proceedings, R&D Productivity: New Challenges for the U.S. Space Program, University of Houston, Clear Lake, Sept. 10, 1985, describes in general terms the modular architecture used in the present invention, and, in FIG. 7, gives an overview of the present invention.
Malek, D. and McIntire, G., "The Marriage of Ada and an Adaptable Multiprocessor Architecture", Proceedings of the 3rd Annual National Conference on Ada Technology, Mar. 20-21, 1985, Fort Monmouth, N.J., discusses use of the Ada programming language with modular computer architecture components as used in the present invention; and gives a general description of the split cycle synchronous bus, P board, M board, D board, and I board of the present invention.